Interrupting a memory built-in self-test

A system, comprising:

• a host device configured to:
• obtain a request to interrupt a memory built-in self-test associated with a memory device;
• determine whether the request to interrupt the memory built-in self-test indicates to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a test mode or while the memory built-in self-test is being performed using a repair mode,
• wherein the test mode has a first duration and the repair mode has a second duration that is shorter than the first duration;
• and
• selectively transmit a mode register write command to write one or more bits, to a mode register of the memory device, that indicate to interrupt the memory built-in self-test, based on determining whether the request to interrupt the memory built-in self-test indicates to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode or while the memory built-in self-test is being performed using the repair mode;
• and
• the memory device, wherein the memory device is configured to:
• read the one or more bits from the mode register of the memory device;
• and
• selectively interrupt the memory built-in self-test, based on the one or more bits, while the memory built-in self-test is being performed using the test mode.

A method, comprising:

• reading one or more bits, associated with a memory built-in self-test, that are stored in a mode register of a memory device;
• identifying, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode,
• wherein the test mode has a first duration and a repair mode associated with the memory built-in self-test has a second duration that is shorter than the first duration;
• and
• interrupting the memory built-in self-test while the memory built-in self-test is being performed using the test mode.