Operations on partially programmed erase blocks

An apparatus, comprising:

• a memory array comprising a plurality of erase blocks, wherein the plurality of erase blocks comprise a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block, a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block, and a third group of memory cells coupled to a third group of access lines and corresponding to a third erase block;
• and
• a controller coupled to the memory array and configured to:
• determine that a sensing operation request is for data stored in the first group of memory cells on a first access line of the first group of access lines corresponding to the first erase block, wherein the first erase block is partially programmed;
• and
• in response to the first erase block being a good erase block and the second and third erase blocks being bad erase blocks:
• apply a first sensing voltage to the first access line during a first sensing operation on the first access line;
• apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation;
• and
• apply a second pass voltage to a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation, to the second group of access lines corresponding to the second erase block during the first sensing operation, and to the third group of access lines corresponding to the third erase block during the first sensing operation.

A method, comprising:

• performing a first sensing operation on a first access line of a first group of word lines of a first erase block that is partially programmed in a memory array, wherein the memory array includes the first erase block comprising a first group of memory cells coupled to the first group of access lines and a second erase block comprising a second group of memory cells coupled to a second group of access lines,
• wherein performing the first sensing operation includes:
• applying a first sensing voltage to the first access line during a first sensing operation on the first access line;
• applying a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation;
• and
• applying a second pass voltage to a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation;
• and
• performing a second sensing operation on a second access line of the second group of access lines corresponding to the second erase block that is partially programmed.