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US 12,738,322 B2Granted
Apparatus and methods for modifying impedances in time-based vector-matrix multiplication circuits
AssigneeSanDisk Technologies LLC
InventorsMohammad Mahmoodi, Zahra Fahimi, Martin Lueker-Boden
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Abstract
An apparatus is provided that includes a memory array including non-volatile memory cells configured to store weights of an artificial neural network, a bit line coupled to a plurality of the non-volatile memory cells, and an interface circuit coupled to the bit line, the interface circuit configured to amplify an output impedance of the memory array.
Claims20
An apparatus comprising:
- a memory array comprising non-volatile memory cells configured to store weights of an artificial neural network;
- a bit line coupled to a plurality of the non-volatile memory cells;
- and
- an interface circuit coupled to the bit line, the interface circuit configured to amplify an output impedance of the memory array.
1 more element
An apparatus comprising
- an array of vertical NAND strings, each comprising a plurality of non-volatile memory cells, each non-volatile memory cell configured to conduct a current based on a corresponding weight of a neuromorphic computing system;
- a plurality of bit lines, each coupled to a corresponding plurality of the vertical NAND strings;
- and
- a plurality of sense amplifiers, each coupled to a corresponding bit line,
- wherein each sense amplifier comprises:
- a capacitor configured to integrate a current conducted by the corresponding bit line;
- and
- a resistive circuit element configured to reduce an input impedance of the sense amplifier.
5 more elements
A method comprising:
- performing a time-based vector-matrix multiplication by:
- programming a current in each memory cell of a 3D NAND memory array, the 3D NAND memory array comprising a first output impedance and a plurality of NAND strings coupled to a bit line;
- coupling a cascode-configured transistor to the bit line, the cascode-configured transistor comprising a second output impedance greater than the first output impedance;
- and
- coupling the cascode-configured transistor to an input of a sense amplifier comprising an integration capacitor disposed in parallel with a resistor,
- wherein an input resistance of the sense amplifier substantially equals a resistance of the resistor.
3 more elements
Dependencies are inferred from the claim text.