Methods to reduce Vpass disturb in 3D NAND memory

A memory device, comprising:

• a memory array comprising blocks, wherein each block includes first memory cells and second memory cells, wherein the first memory cells and the second memory cells are connected in series to a bit line;
• a word line driver;
• and
• a controller configured to control the word line driver to:
• performing a programming operation on a memory cell in the first memory cells,
• wherein the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, wherein the first word lines comprises first unselected word lines of the first memory cells adjacent to the selected word line in a first direction, and
• wherein performing the programming operation comprises:
• applying a programming voltage signal to the selected word line to program the memory cell into a target state;
• applying a first pass voltage to the first unselected word lines;
• applying a second pass voltage to second unselected word lines of the first memory cells adjacent to the selected word line in a second direction;
• and and
• applying a third pass voltage to second word lines corresponding to the second memory cells, wherein the second unselected word lines are adjacent to the second word lines, and wherein the third pass voltage is lower than the first pass voltage.

A memory system, comprising:

• a controller;
• and
• a memory device coupled to the controller, the memory device comprising:
• a memory array comprising blocks, wherein each block includes first memory cells and second memory cells, wherein the first memory cells and the second memory cells are connected in series to a bit line;
• a word line driver;
• and
• a controller configured to control the word line driver to:
• performing a programming operation on a memory cell in the first memory cells, wherein the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, wherein the first word lines comprises first unselected word lines of the first memory cells adjacent to the selected word line in a first direction, and
• wherein performing the programming operation comprises:
• applying a programming voltage signal to the selected word line to program the memory cell into a target state;
• applying a first pass voltage to the first unselected word lines;
• applying a second pass voltage to second unselected word lines of the first memory cells adjacent to the selected word line in a second direction;
• and
• applying a third pass voltage to second word lines corresponding to the second memory cells, wherein the second unselected word lines are adjacent to the second word lines, and wherein the third pass voltage is lower than the first pass voltage.