Charge pump circuit and charge pump device

A charge pump device comprising:

• a plurality stages of charge pump circuit, and an input terminal of a latter stage being connected to an output terminal of a previous stage:
• wherein a first stage of charge pump circuit comprises:
• an input terminal;
• an output terminal;
• a first pump unit comprising:
• a first capacitor having a first terminal configured to receive a first clock signal, and a second terminal;
• a second capacitor having a first terminal configured to receive a second clock signal, and a second terminal;
• a first transistor having a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the first capacitor, and a control terminal coupled to the second terminal of the second capacitor;
• a second transistor having a first terminal coupled to the second terminal of the second capacitor, a second terminal coupled to the second terminal of the first transistor, and a control terminal;
• and
• a first auxiliary control unit coupled to the control terminal of the second transistor, and configured to turn off the second transistor when the first clock signal is at a first high voltage, and turn on the second transistor when the first clock signal is at a low voltage;
• a second pump unit comprising:
• a third capacitor having a first terminal configured to receive a third clock signal, and a second terminal;
• a fourth capacitor having a first terminal configured to receive a fourth clock signal, and a second terminal;
• a third transistor having a first terminal coupled to the input terminal, a second terminal coupled to the second terminal of the third capacitor, and a control terminal coupled to the second terminal of the fourth capacitor;
• a fourth transistor having a first terminal coupled to the second terminal of the fourth capacitor, a second terminal coupled to the second terminal of the third transistor, and a control terminal;
• and
• a second auxiliary control unit coupled to the control terminal of the fourth transistor, and configured to turn off the fourth transistor when the third clock signal is at the first high voltage, and turn on the fourth transistor when the third clock signal is at the low voltage;
• a first output transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of the third transistor;
• a second output transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the output terminal, and a control terminal coupled to the second terminal of the first transistor;
• wherein the first clock signal and the second clock signal are in phase, the first clock signal swings between the low voltage and the first high voltage, and the second clock signal swings between the low voltage and a second high voltage higher than the first high voltage;
• wherein the first clock signal and the third clock signal are out of phase, and the third clock and the fourth clock signal are in phase;
• wherein the third clock signal swings between the low voltage and the first high voltage, and the fourth clock signal swings between the low voltage and the second high voltage;
• wherein the first output transistor is configured to be turned on to generate an output voltage according to a voltage at the second terminal of the first transistor when the first clock signal is at the low voltage, and turned off when the first clock signal is at the first high voltage;
• and
• wherein the second output transistor is configured to be turned on to generate the output voltage according to a voltage at the second terminal of the third transistor when the third clock signal is at the low voltage, and turned off when the third clock signal is at the first high voltage.