US 12,738,313 B2 · In-memory compute SRAM with integrated toggle/copy operation and reconfigurable logic operations

Abstract

Embodiments herein relate to circuitry which allows data to be processed and written back within an SRAM device. In a toggle operation, a memory cell is read and the bit at the complementary output node of a sense amplifier is written back to the memory cell. In a copy operation, a memory cell is read and the bit at the primary output node of the sense amplifier is written to another memory cell in the column. In another aspect, logic operations such as AND, OR, majority, AND-OR, OR-AND, and associated inverse operations can be performed within the SRAM device. This can involve writing data to one or more control memory cells in the same column as the data memory cells involved in the logic operation, and setting the respective word lines to be active concurrently.

Claims18

Dependent claims

An apparatus, comprising:

a sense amplifier coupled to a primary bit line and a complementary bit line of first and second data memory cells and a first control memory cell in a common column, wherein first and second data word lines are coupled to the first and second data memory cells, respectively, and a first control word line is coupled to the first control memory cell;
and
a control circuit coupled to the sense amplifier, the control circuit to perform a logic operation involving bits in the first and second data memory cells, wherein to perform the logic operation, the control circuit is to concurrently activate the first and second data word lines and the first control word line and to receive a bit comprising a result of the logic operation from the sense amplifier, wherein the result corresponds to a majority value resolved by the sense amplifier for the first, second, and control memory cells.

An apparatus, comprising:

a memory device to store instructions;
and
a processor to execute the instructions to perform a logic operation involving bits in first, second and third data memory cells, wherein:
the first, second and third data memory cells are in a common column with first and second control memory cells;
first, second and third data word lines are coupled to the first, second and third data memory cells, respectively;
first and second control word lines are coupled to the first and second control memory cells, respectively;
and
to perform the logic operation, the processor is to write data to the first and second control memory cells based on the logic operation, concurrently activate the first, second and third data word lines and the first and second control word lines, and receive a bit comprising a result of the logic operation from a sense amplifier, wherein the result corresponds to a majority value resolved by the sense amplifier for the first, second, third, first control, and second control memory cells.

5 more elements

Dependencies are inferred from the claim text.

In-memory compute SRAM with integrated toggle/copy operation and reconfigurable logic operations

Life of this patent

In-memory compute SRAM with integrated toggle/copy operation and reconfigurable logic operations

Life of this patent

Abstract

Claims18