Memory device and method with two refresh cycles
AssigneeSK hynix Inc.
InventorSaeng Hwan Kim
Life of this patent
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Abstract
A memory device includes a memory cell array including row-hammer cells configured to store a number of accesses of a corresponding row of a plurality of rows; an address control circuit configured to generate consecutive first and second refresh addresses according to a normal refresh command, wherein the first refresh address indicates an odd-numbered row during a first refresh cycle and an even-numbered row during a second refresh cycle; and a refresh control circuit configured to refresh, according to the normal refresh command, first and second rows respectively corresponding to the first and second refresh addresses and selectively initialize the row-hammer cells of the first row while refreshing the first row.
Claims22
A memory device comprising:
- a memory cell array including a plurality of rows each of which is coupled to row-hammer cells configured to store a number of accesses of a corresponding row of the plurality of rows;
- an address control circuit configured to generate consecutive first and second refresh addresses according to a single normal refresh command, wherein the first refresh address indicates an odd-numbered row during a first refresh cycle and an even-numbered row during a second refresh cycle;
- and
- a refresh control circuit configured to refresh, according to the single normal refresh command, first and second rows respectively corresponding to the first and second refresh addresses and selectively initialize the row-hammer cells of the first row while refreshing the first row.
A memory device comprising:
- a memory cell array including a plurality of rows each of which is coupled to row-hammer cells configured to store a number of accesses of a corresponding row of the plurality of rows;
- an address control circuit configured to generate consecutive 2k refresh addresses according to a single normal refresh command, wherein the refresh addresses start from a starting refresh address indicating an n-th row during a first refresh cycle and a (n+k)-th row during a second refresh cycle;
- and
- a refresh control circuit configured to sequentially refresh, according to the single normal refresh command, 2k rows respectively corresponding to the 2k refresh addresses and selectively initialize the row-hammer cells of k rows among the 2k rows while first refreshing the k rows,
- wherein each of n and k is an integer greater than or equal to 1.
An operating method of a memory device including a plurality of rows each of which is coupled to row-hammer cells configured to store a number of accesses of a corresponding row of the plurality of rows, the operating method comprising:
- repeatedly performing, according to a single normal refresh command during a first refresh cycle, an operation of sequentially refreshing two consecutive rows starting from an odd-numbered row of the rows while selectively initializing the row-hammer cells of the odd-numbered row;
- and
- repeatedly performing, according to the single normal refresh command during a second refresh cycle, an operation of sequentially refreshing two consecutive rows starting from an even-numbered row of the rows while selectively initializing the row-hammer cells of the even-numbered row.
An operating method of a memory device including a plurality of rows each of which is coupled to row-hammer cells configured to store a number of accesses of a corresponding row of the plurality of rows, the operating method comprising:
- repeatedly performing, according to a single normal refresh command during a first refresh cycle, an operation of sequentially refreshing consecutive 2k rows starting from an n-th row while selectively initializing row-hammer cells of k rows that are first refreshed among the 2k rows starting from the n-th row;
- and
- repeatedly performing, according to the single normal refresh command during a second refresh cycle, an operation of sequentially refreshing consecutive 2k rows starting from a (n+k)-th row while selectively initializing row-hammer cells of k rows that are first refreshed among the 2k rows starting from the (n+k)-th row,
- wherein each of k and n is an integer greater than or equal to 1.
Dependencies are inferred from the claim text.