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US 12,738,308 B2Granted
Semiconductor memory device and method for controlling semiconductor memory device
AssigneeRamxeed Limited
InventorKuninori Kawabata
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a sense amplifier configured to amplify a difference between data from a first memory cell and data from a second memory cell, a first restoration circuit configured to output, to a first plate line, a level obtained by inverting a first logic level of data on a first bit line, and a second restoration circuit configured to output, to a second plate line, a level obtained by inverting a second logic level of data on a second bit line.
Claims11
A semiconductor memory device comprising:
- at least one first memory cell and at least one second memory cell each of which includes a ferroelectric capacitor configured to hold data;
- a first bit line and a first plate line that are coupled to the first memory cell;
- a second bit line and a second plate line that are coupled to the second memory cell;
- a sense amplifier configured to amplify a difference between (i) the data that is read out of the first memory cell upon driving the first plate line and (ii) the data that is read out of the second memory cell upon driving the second plate line;
- a first restoration circuit configured to output, to the first plate line, a level obtained by inverting a first logic level of the data on the first bit line, the first logic level being obtained by performing differential amplification through the sense amplifier;
- and
- a second restoration circuit configured to output, to the second plate line, a level obtained by inverting a second logic level of the data on the second bit line, the second logic level being obtained by performing the differential amplification through the sense amplifier.
4 more elements
A semiconductor memory device comprising:
- a first memory cell and a second memory cell each of which includes a ferroelectric capacitor configured to hold data;
- a first bit line and a first plate line that are coupled to the first memory cell;
- a second bit line and a second plate line that coupled to the second memory cell;
- at least one first reference cell coupled to the first bit line and the first plate line, and exclusively coupled to the first memory cell, the first reference cell including a ferroelectric capacitor configured to hold reference data;
- at least one second reference cell coupled to the second bit line and the second plate line, and exclusively coupled to the second memory cell, the second reference cell including a ferroelectric capacitor configured to hold reference data;
- a third plate line coupled to the first reference cell;
- a fourth plate line coupled to the second reference cell;
- a first reset switch configured to reset the first bit line to a low level;
- a second reset switch configured to reset the second bit line to the low level;
- a sense amplifier configured to
- amplify a difference between (i) the data that is read out of the first memory cell to the first bit line upon driving the first plate line and (ii) the reference data that is read out of the second reference cell to the second bit line upon driving the second plate line, or
- amplify a difference between (i) the data that is read out of the second memory cell to the second bit line upon driving the second plate line and (ii) the reference data that is read out of the first reference cell to the first bit line upon driving the first plate line;
- a first restoration circuit configured to output, to the first plate line, a data level obtained by inverting a logic level of the data on the first bit line that is obtained by perform differential amplification through the sense amplifier;
- and
- a second restoration circuit configured to output, to the second plate line, a data level obtained by inverting a logic level of the data on the second bit line that is obtained by performing the differential amplification through the sense amplifier,
- wherein during a read cycle period in which the data is read out of the first memory cell or the second memory cell,
- data “0” is configured to be restored to the second reference cell upon occurrence of a condition in which before reading the data out of the first memory cell to the first bit line, the fourth plate line is set to a high level and the second reset switch is turned on, or
- the data “0” is configured to be restored to the first reference cell upon occurrence of a condition in which before reading the data out of the second memory cell to the second bit line, the third plate line is set to the high level and the first reset switch is turned on.
15 more elements
A method for controlling a semiconductor memory device that includes
- a first memory cell and a second memory cell each of which includes a ferroelectric capacitor for holding data,
- a first bit line and a first plate line that are coupled to the first memory cell, and
- a second bit line and a second plate line that are coupled to the second memory cell, the method comprising:
- amplifying a difference between the data that is read out of the first memory cell to the first bit line upon driving the first plate line and the data that is read out of the second memory cell to the second bit line upon driving the second plate line;
- outputting, to the first plate line, a first level that is obtained by inverting a logic level of the data on the first bit line, the first logic level being obtained by performing differential amplification;
- and
- outputting, to the second plate line, a second level that is obtained by inverting a second logic level of the data on the second bit line, the second logic level being obtained by performing the differential amplification.
4 more elements
Dependencies are inferred from the claim text.