Decision feedback equalizer, and memory device and memory system including the same

A memory device comprising:

• a decision feedback equalizer (DFE) configured to receive an input signal and output first and second internal signals,
• wherein the DFE comprises:
• an adder including a first node and a second node, and the adder configured to:
• receive the input signal,
• amplify a voltage difference between a reference voltage level and a voltage level of the input signal based on a DQ bias voltage, and
• output the first internal signal from the first node and the second internal signal from the second node;
• a first DFE tap configured to provide a first tap bias current to one of the first node and the second node, based on a first sample signal corresponding to an immediately preceding bit of the input signal;
• and
• a tap bias voltage generation circuit configured to provide the first DFE tap with a first tap bias voltage corresponding to the first tap bias current, based on the DQ bias voltage, a tap code set in a training operation of the memory device, and a temperature code depending on a temperature of the memory device.

A memory system comprising:

• a memory controller;
• and
• a memory device connected to the memory controller,
• wherein the memory device comprises a decision feedback equalizer (DFE), and
• wherein the DFE is configured to receive an input signal and output first and second internal signals, and the DFE comprises:
• an adder including a first node and a second node, and the adder configured to:
• receive the input signal,
• amplify a voltage difference between a reference voltage level and a voltage level of the input signal based on a DQ bias voltage, and
• output the first internal signal from the first node and the second internal signal from the second node;
• a first DFE tap configured to provide a first tap bias current to one of the first node and the second node, based on a first sample signal corresponding to an immediately preceding bit of the input signal;
• and
• a tap bias voltage generation circuit configured to provide the first DFE tap with a first tap bias voltage corresponding to the first tap bias current, based on the DQ bias voltage, a tap code set in a training operation of the memory system, and a temperature code depending on a temperature of the memory system.