Display panel having a shift register with a plurality of group stages and driving method thereof

A display panel, comprising a gate driving circuit, wherein

• the gate driving circuit comprises shift registers of a plurality of stages arranged in sequence, the shift registers of the plurality of stages arranged in sequence are combined into N groups of gate driving sub-circuits, and shift registers in the N groups of gate driving sub-circuits are cascaded, respectively;
• an m-th group of gate driving sub-circuits in the N groups of gate driving sub-circuits comprises a shift register of an m-th stage and a shift register of an (m+L*N)-th stage that are cascaded,
• wherein m is an integer that is greater than or equal to 1 and less than or equal to N, L is an integer that is greater than or equal to 1, and N is an even number that is greater than or equal to 2;
• wherein the display panel further comprises 4K clock signal lines,
• wherein the 4K clock signal lines comprise a first clock signal line to a (4K)-th clock signal line, which are connected to clock signal terminals of the shift registers of the plurality of stages, respectively, to provide clock signals,
• wherein K is an integer that is greater than or equal to 1;
• wherein the display panel further comprises:
• a clock controller, which is connected to the 4K clock signal lines and is configured to:
• upon providing clock signals to clock signal lines connected to odd-numbered groups of gate driving sub-circuits in the N groups of gate driving sub-circuits, not provide the clock signals to clock signal lines connected to even-numbered groups of gate driving sub-circuits in the N groups of gate driving sub-circuits or provide invalid clock signals to the clock signal lines connected to the even-numbered groups of gate driving sub-circuits;
• and
• upon providing the clock signals to the clock signal lines connected to the even-numbered groups of gate driving sub-circuits, not provide the clock signals to the clock signal lines connected to the odd-numbered groups of gate driving sub-circuits or provide the invalid clock signals to the clock signal lines connected to the odd-numbered groups of gate driving sub-circuits;
• wherein the display panel further comprises:
• a pixel array which is connected to the gate driving circuit, a data driving circuit and a plurality of data lines;
• wherein the pixel array comprises a plurality of rows of sub-pixels and a plurality of columns of sub-pixels;
• the plurality of data lines are electrically connected to the plurality of columns of sub-pixels, and are configured to transmit data signals provided by the data driving circuit to the plurality of columns of sub-pixels;
• wherein the data driving circuit is configured to:
• upon the pixel array being driven to display an x-th frame of pattern, provide a data signal with a first level to the plurality of data lines;
• and
• upon the pixel array being driven to display an (x+1)-th frame of pattern, provide a data signal with a second level to the plurality of data lines;
• and
• wherein x is an integer greater than or equal to 1.