Scanning signal line drive circuit and display device provided with same

A scanning signal line drive circuit configured to drive a plurality of scanning signal lines arranged in a display portion of a display device, the scanning signal line drive circuit comprising:

• a plurality of unit circuits connected in cascade to form a shift register,
• wherein the shift register operates based on a multi-phase clock signal,
• the multi-phase clock signal includes a plurality of clock signals cyclically corresponding to the plurality of unit circuits,
• a pulse of one of two clock signals adjacent to each other, among the plurality of clock signals partially overlaps a pulse of another one of the two clock signals,
• the plurality of unit circuits respectively corresponds to the plurality of scanning signal lines,
• each unit circuit is configured to determine a state of the unit circuit based on a set signal and a reset signal provided as input signals, and includes:
• an internal node configured to selectively hold voltages of a first logic level and a second logic level indicating states of each unit circuit,
• a set circuit configured to apply a voltage of the first logic level to the internal node when the set signal is active,
• a reset circuit configured to apply a voltage of the second logic level to the internal node when the reset signal is active,
• an output circuit including an output transistor that is in an on state when the voltage of the first logic level is held in the internal node, and that is in an off state when the voltage of the second logic level is held in the internal node,
• a clock input terminal for receiving a corresponding clock signal among the plurality of clock signals, and
• an output terminal connected to a corresponding scanning signal line among the plurality of scanning signal lines and connected to the clock input terminal via the output transistor,
• the reset circuit includes a reset transistor including a drain terminal that is connected to the internal node, a source terminal, and a gate terminal to which the reset signal is supplied,
• the output circuit outputs a scanning signal, based on the corresponding clock signal, from the output terminal to the corresponding scanning signal line, and
• the shift register is configured, such that, in each unit circuit:
• a voltage signal is supplied to the source terminal of the reset transistor as a reset state voltage signal, the voltage signal maintaining an active voltage level corresponding to an active state of the reset signal when the reset signal changes from an inactive state to the active state, and changing from the active voltage level to the second logic level before the reset signal changes from the active state to the inactive state,
• a scanning signal, output from a subsequent unit circuit in a stage subsequent to a current stage, is supplied to the source terminal of the reset transistor as the reset state voltage signal, and
• a scanning signal, output from a unit circuit subsequent to the subsequent unit circuit, is supplied to the gate terminal of the reset transistor as the reset signal.