Display panel and display device

A display panel, comprising a shift register, wherein:

• the shift register includes a plurality of shift register units, wherein a shift register unit of the plurality of shift register units includes an input circuit, an output circuit and a voltage stabilization circuit;
• the shift register unit further includes an input terminal, a first clock terminal, a first auxiliary voltage terminal, a first voltage terminal, a second voltage terminal, a third voltage terminal and an output terminal;
• the input circuit is electrically connected to the input terminal, the first clock terminal, a first node and a second node respectively, and the input circuit is configured to control a signal of the first node and a signal of the second node according to an input signal of the input terminal and a first clock signal of the first clock terminal;
• the voltage stabilization circuit is electrically connected to the first auxiliary voltage terminal, the first voltage terminal, the first node and a third node respectively, and the voltage stabilization circuit is configured to control a transmission path between the first node and the third node according to a signal of the first auxiliary voltage terminal, a signal of the first voltage terminal and a signal of the third node;
• the output circuit is electrically connected to the second voltage terminal, the third voltage terminal, the third node, the second node, and the output terminal respectively, and the output circuit is configured to control the output terminal to output a first output signal according to the signal of the third node and the signal of the second node;
• the voltage stabilization circuit includes a first voltage stabilization transistor and a first auxiliary transistor;
• a first electrode of the first voltage stabilization transistor is electrically connected to the first node, a second electrode of the first voltage stabilization transistor is electrically connected to the third node, and a gate of the first voltage stabilization transistor is electrically connected to the first voltage terminal;
• a first electrode of the first auxiliary transistor is electrically connected to the first auxiliary voltage terminal, and a second electrode of the first auxiliary transistor and the first electrode of the first voltage stabilization transistor are electrically connected to a first auxiliary node, and a gate of the first auxiliary transistor is electrically connected to the third node;
• and
• during at least a part of a period when the signal of the third node is at an enable level, the first node and the third node are cut off from each other.

A display device, including a display panel, wherein the display panel includes a shift register, wherein:

• the shift register includes a plurality of shift register units, wherein a shift register unit of the plurality of shift register units includes an input circuit, an output circuit and a voltage stabilization circuit;
• the shift register unit further includes an input terminal, a first clock terminal, a first auxiliary voltage terminal, a first voltage terminal, a second voltage terminal, a third voltage terminal and an output terminal;
• the input circuit is electrically connected to the input terminal, the first clock terminal, a first node and a second node respectively, and the input circuit is configured to control a signal of the first node and a signal of the second node according to an input signal of the input terminal and a first clock signal of the first clock terminal;
• the voltage stabilization circuit includes a first voltage stabilization transistor and a first auxiliary transistor and is electrically connected to the first auxiliary voltage terminal, the first voltage terminal, the first node and a third node respectively, and the voltage stabilization circuit is configured to control a transmission path between the first node and the third node according to a signal of the first auxiliary voltage terminal, a signal of the first voltage terminal and a signal of the third node;
• the output circuit is electrically connected to the second voltage terminal, the third voltage terminal, the third node, the second node, and the output terminal respectively, and the output circuit is configured to control the output terminal to output a first output signal according to the signal of the third node and the signal of the second node;
• and
• during at least a part of a period when the signal of the third node is at an enable level, the first node and the third node are cut off from each other by the voltage stabilization circuit in response to the signal of the third node being at the enable level controlling the first auxiliary transistor to be turned on.