Back to results
US 12,738,202 B2Granted
Timing controller and display device including the same
AssigneeLG Display Co., Ltd.
InventorKyeong Min Moon
Life of this patent
Estimating the term…
Abstract
Disclosed is a timing controller and a display device including the same. More specifically, the present disclosure relates to a timing controller which unequally sets a pulse width modulation (PWM) pulse width of each of one or more subframes corresponding to a gray level value of pixel data, thereby allowing the luminance of a display device to nonlinearly increase, and a display device including the same.
Claims17
A timing controller comprising:
- a memory configured to store a plurality of subframe information obtained by time-dividing a unit frame period;
- a data analysis circuit configured to receive input image data from a host and check one pixel gray value which is a gray level value of one pixel data included in the input image data;
- and
- a pulse width setting circuit configured to set a pulse width modulation (PWM) pulse width of each of one or more subframes corresponding to the one pixel gray value unequally per each subframe,
- wherein the memory is configured to further store a pulse width increase amount for preset gray level values in a lookup table, and
- wherein the pulse width increase amount gradually increases as a gray level value in a low gray level section increases to a specific gray level value.
3 more elements
A timing controller comprising:
- a memory configured to store a plurality of subframe information obtained by time-dividing a unit frame period;
- a data analysis circuit configured to receive input image data from a host and check one pixel gray value which is a gray level value of one pixel data included in the input image data;
- and
- a pulse width setting circuit configured to set a pulse width modulation (PWM) pulse width of each of one or more subframes corresponding to the one pixel gray value unequally per each subframe,
- wherein the pulse width setting circuit is configured to calculate one pixel gray level value and a pulse width increase amount for each of grays values that are lower than the one pixel gray level value using a following equation:
- dPW
-
- (
- Gray
- )
- =
- (
- Gray
- Gray
- Max
- )
- Gamma
- -
- (
- Gray
- -
- 1
- Gray
- Max
- )
- Gamma
- (
- Gray_Tap
-
- (
- n
- +
- 1
- )
- Gray
- Max
- )
- Gamma
- -
- (
- Gray_Tap
-
- (
- n
- )
- Gray
- Max
- )
- Gamma
- wherein, “Gray” denotes a target gray level value of which the pulse width increase amount is to be calculated,
- “dPW(Gray)” denotes a pulse width increase amount of the target gray level value,
- “GrayMax” denotes the maximum gray level value,
- “Gamma” denotes a gamma curve value,
- “Gray−1” denotes a gray level value that is smaller than the target gray level value by one gray level,
- “Gray_Tap(n+1)” denotes a critical gray level value of a gray level section including the target gray level value, and
- “Gray_Tap(n)” denotes a critical gray level value of a gray level section that is lower than the gray level section including the target gray level value.
53 more elements
A display device comprising:
- a gate driver configured to supply a scan signal to scan lines of a display panel in response to a gate control signal;
- and
- a timing controller configured to time-divide a unit frame period, which is a period for displaying one image, into a plurality of subframes, unequally set a pulse width modulation (PWM) pulse width of each of one or more subframes, which corresponds to one pixel gray level value data which is a gray level value of one pixel data included in input image data received, and allow the PWM pulse width for each subframe set for each of the one or more subframes to be included in the gate control signal to supply the PWM pulse width to the gate driver,
- wherein the timing controller includes:
- a memory configured to store a plurality of subframe information obtained by time-dividing a unit frame period;
- a data analysis circuit configured to receive input image data from a host and check one pixel gray value which is a gray level value of one pixel data included in the input image data;
- and
- a pulse width setting circuit configured to set a pulse width modulation (PWM) pulse width of each of one or more subframes corresponding to the one pixel gray value unequally per each subframe,
- wherein the memory is configured to further store a pulse width increase amount for preset gray level values in a lookup table, and
- wherein the pulse width increase amount gradually increases as a gray level value in a low gray level section increases to a specific gray level value.
7 more elements
Dependencies are inferred from the claim text.