Display device and electronic device

A display device comprising:

• a pixel, the pixel comprising:
• a first transistor;
• a second transistor;
• a third transistor;
• a fourth transistor;
• a fifth transistor;
• a sixth transistor;
• a capacitor;
• and
• a light-emitting device,
• wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, and one electrode of the capacitor,
• wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the light-emitting device and the other electrode of the capacitor,
• wherein a first data potential is charged in the gate of the first transistor through the second transistor,
• wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and a gate of the third transistor,
• wherein a gate of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor,
• wherein the other of the source and the drain of the fourth transistor is electrically connected to a first wiring, and
• wherein the other of the source and the drain of the sixth transistor is electrically connected to a second wiring supplying a second data potential.

A display device comprising:

• a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
• a first capacitor;
• a second capacitor;
• and
• a light-emitting device,
• wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor, one of a source and a drain of the third transistor, and one electrode of the first capacitor,
• wherein one of a source and a drain of the first transistor is electrically connected to one electrode of the light-emitting device and the other electrode of the first capacitor,
• wherein a first data potential is supplied to the other of the source and the drain of the second transistor,
• wherein a gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and one of a source and a drain of the fifth transistor,
• wherein a gate of the fourth transistor is electrically connected to one of a source and a drain of the sixth transistor and one electrode of the second capacitor,
• wherein the other of the source and the drain of the fourth transistor is electrically connected to a first wiring supplying a slope signal, and
• wherein the other of the source and the drain of the sixth transistor is electrically connected to a second wiring supplying a second data potential.