US 12,737,606 B2 · Systems and methods of sparsity exploiting

Abstract

Disclosed is a neuromorphic integrated circuit including, in some embodiments, a multi-layered neural network disposed in an analog multiplier array of two-quadrant multipliers. Each multiplier of the multipliers is wired to ground and draws a negligible amount of current when input signal values for input signals to transistors of the multiplier are approximately zero, weight values of the transistors of the multiplier are approximately zero, or a combination thereof Also disclosed is a method of the neuromorphic integrated circuit including, in some embodiments, training the neural network; tracking rates of change for the weight values; determining if and how quickly certain weight values are trending toward zero; and driving those weight values toward zero, thereby encouraging sparsity in the neural network. Sparsity in the neural network combined with the multipliers wired to ground minimizes power consumption of the neuromorphic integrated circuit such that battery power is sufficient for power.

Claims18

Dependent claims

A neuromorphic integrated circuit, comprising:

a multi-layered neural network disposed in an analog multiplier array of a plurality of two-quadrant multipliers arranged in a memory sector of the neuromorphic integrated circuit, wherein at least one of the plurality of two-quadrant multipliers is a bias-free two-quadrant multiplier,
wherein each multiplier of the multipliers is wired to ground and draws a reduced amount of current when input signal values for input signals to transistors of the multiplier are near zero or zero, weight values of the transistors of the multiplier are near zero or zero, or a combination thereof,
wherein each bias-free two-quadrant multiplier of the two-quadrant multipliers has a differential structure configured to allow programmatic compensation for overshoot if any one of two cells is set with a higher weight value than targeted;
and
wherein the differential structure is coupled to current-sensing circuitry comprising at least one of a current mirror, a charge integrator, or a transimpedance amplifier.

2 more elements

A method for compensation for overshoot in a neuromorphic integrated circuit, comprising:

training a multi-layered neural network disposed in an analog multiplier array of a plurality of two-quadrant multipliers in a memory sector of the neuromorphic integrated circuit, wherein at least one of the plurality of two-quadrant multipliers is a bias-free two-quadrant multiplier,
wherein each multiplier of the multipliers is wired to ground and draws a first amount of current when input signal values for input signals to transistors of the multiplier are near zero or zero, weight values of the transistors of the multiplier are near zero or zero, or a combination thereof;
wherein each bias-free two-quadrant multiplier of the two-quadrant multipliers has a differential structure configured to allow programmatic compensation for overshoot if any one of two cells is set with a higher weight value than targeted;
and
processing a differential current output from the differential structure using current-sensing circuitry comprising at least one of a current mirror, a charge integrator, or a transimpedance amplifier.

2 more elements

Dependencies are inferred from the claim text.

Systems and methods of sparsity exploiting

Life of this patent

Systems and methods of sparsity exploiting

Life of this patent

Abstract

Claims18