Data stream-based computation unit, artificial intelligence chip, and accelerator

A data stream-based computation unit, comprising a plurality of computation circuits, each computation circuit comprising a first input terminal and a second input terminal, wherein,

• M first input terminals of M computation circuits in the plurality of computation circuits are configured to receive M pieces of first data required for performing a computation task on a one-to-one basis, where M≥2 and M is a positive integer;
• M second input terminals of the M computation circuits are configured to receive M pieces of second data distinct from each other required for performing the computation task on a one-to-one basis;
• and
• the M computation circuits are configured to perform the computation task in parallel on the basis of the M pieces of first data and the M pieces of second data, wherein each computation circuit of the M computation circuits is configured to perform the computation task on the basis of one piece of first data and one piece of second data,
• wherein the computation task is a computation in a neural network model,
• wherein the computation task is a convolution, and the M pieces of first data are identical to each other, and
• wherein each piece of first data comprises feature map data corresponding to M pieces of convolution kernel data in a feature map, and each piece of second data comprises one of the M pieces of convolution kernel data.