Embedded-oriented configurable many-core processor

An embedded-oriented configurable many-core processor, comprising:

• an on-chip data-bus system, an on-chip event-bus system, a data connection line, N routing units and N cores,
• the on-chip data-bus system comprises:
• multiple transverse data-bus and multiple vertical data-bus, wherein the multiple transverse data-bus and the multiple vertical data-bus being staggered transversely and vertically to form N intersections, each intersection of the N intersections being correspondingly provided with a routing unit, and adjacent routing units being connected by transverse data-bus or vertical data-bus;
• the on-chip event-bus system comprises:
• N event control units, an event bus and an event signal line;
• one core corresponds to one routing unit and one event control unit, each core of the N cores being connected with the corresponding routing unit through the data connection line, on the one hand, each event control unit being connected with the event bus, and the each event control unit being connected with the corresponding core and routing unit through the event signal line on the other hand, and the event control unit being configured to implement signal gating and logical connection between the event bus and the event signal line;
• wherein the event bus comprises:
• a set of forward event bus for unidirectional transmission and a set of reverse event bus for unidirectional transmission, transmission directions of the forward event bus and the reverse event bus being opposite, and the forward event bus and the reverse event bus being respectively composed of K signal lines;
• the event signal line comprises:
• P output event signal lines and Q input event signal lines;
• wherein the event control unit comprises:
• L output configuration registers, L′ input configuration registers and a total of J*(L+L′) transmission gates arranged into (L+L′) sets, wherein each set comprise J transmission gates, and a set of transmission gates corresponding to an output configuration register or an input configuration register;
• each output configuration register being respectively connected with control terminals of the J transmission gates in the corresponding set of transmission gates through J leads;
• each input configuration register being respectively connected with the control terminals of the J transmission gates in the corresponding set of transmission gates through the J leads;
• input terminals of the J transmission gates in the corresponding set of transmission gates of the output configuration register being respectively connected with K signal lines of the forward event bus and the K signal lines of the reverse event bus, output terminals of the J transmission gates in the corresponding set of transmission gates of the output configuration register being respectively connected with corresponding output event signal lines, that is, J=2K, P=L;
• the output terminals of the J transmission gates in the corresponding set of transmission gates of the input configuration register being respectively connected with the K signal lines of the forward event bus and the K signal lines of the reverse event bus, the input terminals of the J transmission gates in the corresponding set of transmission gates of the input configuration register being respectively connected with corresponding input event signal lines, that is, Q=L′.