Semiconductor memory device with signaled command/address inversion
AssigneeMicron Technology, Inc.
InventorKeun-Soo Song
Life of this patent
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Abstract
Disclosed are methods, systems, and apparatuses for semiconductor memory devices (e.g., dynamic random access memory (DRAM)) that include a command/address inversion (CAI) input signal indicating whether command/address inputs to the memory devices are inverted. The CAI input signal may be generated by a memory controller, a registering clock driver (RCD), or other component coupled to the memory devices, and the component may generate the CAI input signal differently for the different memory devices to which the component is coupled. As described herein, the component may dynamically generate the CAI input signal based on the values of the command/address inputs so as to reduce power consumption by the memory devices while retaining signal integrity.
Claims20
A memory module comprising:
- a plurality of memory devices having termination circuitry;
- a command/address (CA) input;
- and
- a dynamic command/address inversion (CAI) control circuit, the dynamic CAI control circuit configured to:
- evaluate the CA input;
- generate, based on the evaluation of the CA input and the termination circuitry of the plurality of memory devices, a CA output, wherein the CA output comprises a value of the CA input or an inverted value of the CA input such that the CA output lowers a power consumption of the termination circuitry of the plurality of memory devices;
- generate a CAI output, wherein the CAI output indicates whether the CA output comprises the inverted value of the CA input;
- and
- transmit the CA output and the CAI output to the plurality of memory devices.
A memory module comprising:
- a first plurality of memory devices, wherein the first plurality of memory devices have a first on-die termination (ODT) that is one of a VDD-based ODT or a VSS-based ODT;
- a second plurality of memory devices, wherein the second plurality of memory devices have a second ODT that is one of a VDD-based ODT or a VSS-based ODT;
- a command/address (CA) input;
- a first command/address inversion (CAI) input;
- and
- a second CAI input;
- wherein the memory module is configured to:
- determine a first ODT setting for the first plurality of memory devices;
- determine a second ODT setting for the second plurality of memory devices;
- generate a first CA output, comprising a value of the CA input or an inverted value of the CA input, based on the first CAI input and the first ODT setting;
- generate a second CA output, comprising the value of the CA input or the inverted value of the CA input, based on the second CAI input and the second ODT setting;
- transmit the first CA output to the first plurality of memory devices;
- and
- transmit the second CA output to the second plurality of memory devices.
A method comprising:
- receiving, at a memory controller, a request from a host device coupled to the memory controller;
- generating, in response to the received request, a command/address (CA) value characterizing the request, wherein the CA value comprises a plurality of bits;
- determining a number of CA value bits having a binary 0 value to determine whether transmitting the CA value or an inverted CA value reduces power consumption associated with termination circuitry of a memory module;
- generating, based on the determination and based on power characteristics of the termination circuitry, a CA output, wherein the CA output comprises the CA value or the inverted CA value;
- and
- transmitting the CA output to the memory module coupled to the memory controller.
Dependencies are inferred from the claim text.