Virtualized parallel access architecture for flash memory

A data storage device, comprising:

• a flash memory including a plurality of first memory units and a plurality of second memory units;
• and
• a memory controller coupled to and configured to control the flash memory, comprising:
• a parallel accessing control circuit, coupled to a command and address (CA) bus, a first data bus, and a second data bus that are respectively coupled to the plurality of first memory units and the plurality of second memory units, wherein the parallel accessing control circuit comprises:
• a CA sequencer coupled to the CA bus, configured to manage and transmit one or more control signals and one or more memory addresses that are associated with a host command and transmitted over the CA bus;
• a first data input/output (DQ) sequencer coupled to the first data bus, configured to, through the first data bus, transmit a first portion of encoded write data to one of the plurality of first memory units and/or receive a first portion of read encoded data from one of the plurality of first memory units;
• and
• a second DQ sequencer coupled to the second data bus, configured to, through the second data bus, transmit a second portion of the encoded write data to one of the plurality of second memory units and/or receive a second portion of the read encoded data from one of the plurality of second memory units.