Prioritizing entries of an instruction fetch resource after stall-retirement events

A method at a processor core, the method comprising:

• searching multiple entries of an instruction fetch resource to detect a location of a version of a first instruction, wherein the multiple entries each correspond to a different respective instruction, and wherein a first entry of the multiple entries corresponds to the first instruction;
• performing a selection of a victim entry to be evicted from the instruction fetch resource, wherein the selection is performed based on a prioritization scheme while a first one or more entries of the multiple entries are each assigned a first priority level of the prioritization scheme, and while a second one or more entries of the multiple entries are each assigned a second priority level of the prioritization scheme, wherein the victim entry is selected from among only the second one or more entries;
• detecting a retirement event comprising a retirement of the first instruction after a stall of the processor core, wherein the stall is based on the first instruction;
• and
• assigning the first priority level to the first entry based on the retirement event.

A system comprising:

• a processor core comprising:
• an instruction fetch resource comprising multiple entries which are each to correspond to a different respective instruction, wherein a first entry of the multiple entries is to correspond to a first instruction;
• first circuitry to search the multiple entries of the instruction fetch resource to detect a location of a version of the first instruction;
• second circuitry to perform a selection of a victim entry to be evicted from the instruction fetch resource, wherein the selection is performed based on a prioritization scheme while a first one or more entries of the multiple entries are each assigned a first priority level of the prioritization scheme, and while a second one or more entries of the multiple entries are each assigned a second priority level of the prioritization scheme, wherein the victim entry is selected from among only the second one or more entries;
• and
• third circuitry to assign the first priority level to the first entry based on a retirement event comprising a retirement of the first instruction after a stall of the processor core, wherein the stall is based on the first instruction;
• and
• a memory coupled to the processor core, the memory to store instructions comprising the first instruction.