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US 12,737,296 B2Granted
Scalable system on a chip
AssigneeApple Inc.
InventorsPer H. Hammarlund, Lior Zimet, James Vash, Gaurav Garg, Sergio Kolor, Harshavardhan Kaushikkar, Ramesh B. Gunna, Steven R. Hutsell
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Abstract
A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.
Claims20
A system, comprising:
- a plurality of processor cores;
- a plurality of graphics processing units;
- a plurality of peripheral devices distinct from the processor cores and the graphics processing units;
- a plurality of memory controller circuits configured to interface with a system memory;
- and
- an interconnect fabric configured to provide communication between the memory controller circuits and the processor cores, the graphics processing units, and the peripheral devices;
- wherein the processor cores, the graphics processing units, the peripheral devices and the memory controller circuits are configured to communicate via a unified memory architecture in which adjacent blocks of a given page within a unified address space defined by the unified memory architecture are distributed among the plurality of memory controller circuits;
- and
- wherein the processor cores, the graphics processing units, the peripheral devices, the memory controller circuits, and the interconnect fabric are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies.
6 more elements
A method, comprising:
- communicating, via a unified memory architecture, among a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral devices distinct from the plurality of processor cores and the plurality of graphics processing units, and a plurality of memory controller circuits over an interconnect fabric in a system, wherein the processor cores, the graphics processing units, the peripheral devices, the memory controller circuits, and the interconnect fabric are included in a system on a chip (SOC) integrated onto one or more co-packaged semiconductor dies;
- and
- distributing, in the SOC, adjacent blocks of a given page within a unified address space defined by the unified memory architecture among the plurality of memory controller circuits for storage in memory.
Dependencies are inferred from the claim text.