Technique for storing data in a cache

An apparatus comprising:

• cache circuitry providing a plurality of cache lines to store data for access by a processing element;
• and
• cache control circuitry arranged to control storage of data with associated memory addresses in main memory in the cache circuitry, wherein the cache control circuitry is arranged to manage storage of data within the cache circuitry for data blocks of size X exceeding a size of data that is storeable within a single cache line of the cache circuitry;
• wherein the cache control circuitry is arranged, for each data block to be stored in the cache circuitry, to determine in which state of a plurality of states to store that data block in the cache circuitry, the plurality of states comprising an uncompressed state where the data block is stored within a plurality Y of cache lines and at least one compressed state where the data block is represented in a form occupying less than Y cache lines within the cache circuitry,
• wherein the cache control circuitry is arranged to determine in which state of the plurality of states to store that data block in the cache circuitry based on evaluating a current state of data of that data block to determine whether there is any available state that would allow that data block to be stored in a compressed state within the cache occupying fewer cache lines than the current state;
• and
• the cache control circuitry is arranged to maintain a plurality of metadata entries in the main memory, where each metadata entry is associated with a data block of size X and is arranged to identify which state has been chosen by the cache control circuitry to represent that data block when stored in the cache circuitry.