Hinting mechanism for efficient accelerator services
AssigneeSanDisk Technologies LLC
InventorRamanathan Muthiah
Life of this patent
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Abstract
Solid State Drive (SSD) devices with hardware accelerators and methods for apportioning storage resources in the SSD are disclosed. SSDs typically comprise an array of non-volatile memory devices and a controller which manages access to the memory devices. The controller may also comprise one or more accelerators to either improve the performance of the SSD itself or to offload specialized computation workloads of a host-computing device. Different accelerators may be dynamically assigned portions of the non-volatile memory array according to the type of data being accessed and/or the throughput required. Provision is also made for the data to be accessed directly by the accelerators bypassing the controller and for a hinting mechanism to improve accelerator performance.
Claims20
A device, comprising:
- a memory comprising a plurality of non-volatile memory devices;
- and
- an accelerator storage-biasing logic (ASBL);
- a first accelerator configured with a first throughput, wherein the first accelerator sends a first hint to the ASBL wherein the first hint:
- requests a change in a storage management policy for the first accelerator;
- and
- indicates a need for a memory resource in advance of an actual need by the first accelerator by providing timing information about a duration of a task;
- wherein the ASBL makes a first assessment of the first hint and proactively copies data to the memory resource, and assigns a first portion of the memory as a data structure to the first accelerator according to the first throughput and the first accelerator directly accesses the first portion of the memory, bypassing the ASBL.
A method of operating a storage device comprising:
- a storage control unit (SCU) further comprising an accelerator storage-biasing logic (ASBL), a first accelerator, a second accelerator, and a memory, the memory comprising:
- a single bit per cell region and a multiple bits per cell region, the method comprising:
- sending a first hint from the first accelerator to the ASBL, wherein the first hint indicates a need for a memory resource in advance of an actual need by the first accelerator by providing timing information about a duration of a task;
- and
- making a first assessment of the first hint, proactively copying data to the memory resource, and assigning a first portion of the memory as a data structure to the first accelerator according to a first throughput of the first accelerator;
- sending a second hint from the second accelerator to the ASBL;
- and
- determining the throughput needs of the first accelerator and the second accelerator.
A non-transitory computer-readable medium comprising:
- computer-readable code operable, when executed by one or more processing apparatuses in a storage device;
- the storage device comprising a storage control unit (SCU) further comprising an accelerator storage-biasing logic (ASBL), a first accelerator, a second accelerator, and a memory;
- the memory comprising a single bit per cell region and a multiple bits per cell region;
- wherein the computer-readable code instructs the storage device to perform the method of:
- sending a first hint from the first accelerator to the ASBL wherein the first hint indicates a need for a memory resource in advance of an actual need by the first accelerator by providing timing information about a duration of a task;
- making a first assessment of the first hint and proactively copying data to the memory resource;
- sending a second hint from the second accelerator to the ASBL;
- determining the throughput needs of the first accelerator and the second accelerator;
- assigning a first portion of the single bit per cell region of the memory to the first accelerator according to a first throughput of the first accelerator;
- transferring first data from the multiple bits per cell region to the portion of the single bit per cell region;
- and
- operating the first accelerator using the data in the portion of the single bit per cell region, bypassing the ASBL.
Dependencies are inferred from the claim text.