Memory access validation for input/output operations using an interposer
AssigneeAdvanced Micro Devices, Inc.
InventorDavid Joseph Clinton
Life of this patent
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Abstract
Memory access validation for input/output operations using an interposer is described. In one or more implementations, an interposer is disposed logically between an input/output device and a memory. The interposer receives a plurality of requests from the input/output device to access the memory non-sequentially in association with an input/output operation. Responsive to each request, the interposer updates an accumulated error code using error-detection logic. Based upon the accumulated error code, the interposer outputs an I/O validity indicator.
Claims20
A device comprising:
- an interposer disposed logically between an input/output device and a memory to:
- receive a plurality of requests from the input/output device to access the memory non-sequentially in association with an input/output operation;
- responsive to each request of the plurality of requests, incrementally update an accumulated error code based at least in part on an indication of which particular bytes of the memory are requested in each request of the plurality of requests, wherein the accumulated error code is updated incrementally with each request based on at least one error detection algorithm;
- and
- output an input/output validity indicator for the input/output operation based on the accumulated error code.
A system comprising:
- a memory;
- an input/output device to generate a plurality of requests to access the memory non-sequentially in association with an input/output operation;
- and
- an interposer disposed logically between the memory and the input/output device, the interposer having error-detection logic to incrementally update an accumulated error code based at least in part on an indication of which particular bytes of the memory are requested in each request of the plurality of requests and output an input/output validity indicator based on the accumulated error code, wherein the accumulated error code is updated incrementally with each request of the plurality of requests based on at least one error detection algorithm.
A method comprising:
- receiving, by an interposer and from an input/output device, a plurality of requests to access memory non-sequentially in association with an input/output operation;
- responsive to each request of the plurality of requests, incrementally updating an accumulated error code based at least in part on an indication of which particular bytes of the memory are requested in each request of the plurality of requests, wherein the accumulated error code is updated incrementally with each request based on at least one error detection algorithm;
- and
- outputting, by the interposer, an input/output validity indicator based on the accumulated error code.
Dependencies are inferred from the claim text.