Cross drawer message passing in a strongly ordered coherent symmetric multiprocessing (SMP) cache

A computer system comprising;

• a processor set including at least one multicore processor, the at least one multicore processor including a plurality of cores arranged in a plurality of drawers;
• wherein the at least one multicore processor is configured to issue an operation to a first core of a multicore processor, the operation including transmitting a message from the first core to a second core of the multicore processor;
• and
• wherein transmitting the message includes defining a payload including a source address of the message, a destination address of the message and a destination key of the message, providing the payload to a nest fabric of the first core and capturing the source address and the destination address, initiating a fetch to capture the message and store the message in a in a second cache of the second core, removing the message from the first core, and the second core fetching the message from the second cache, and returning a condition code to the first core without pulling the destination address back to the first core.

A computer program product comprising:

• a non-transitory memory storing instructions configured to cause a multicore processor to perform a process including:
• issuing an operation to a first core of the multicore processor, the operation including transmitting a message from the first core to a second core of the multicore processor;
• and
• wherein transmitting the message includes defining a payload including a source address of the message, a destination address of the message and a destination key of the message, providing the payload to a nest fabric of the first core and capturing the source address and the destination address, initiating a fetch to capture the message and store the message in a in a second cache of the second core, removing the message from the first core, and the second core fetching the message from the second cache, and returning a condition code to the first core without pulling the destination address back to the first core.