Schedule instructions of a program of data flows for execution in tiles of a coarse grained reconfigurable array

A method, comprising:

• receiving a program specifying a plurality of memory variables, a plurality of data flows through the memory variables, and first instructions to transform data along the data flows;
• receiving a profile specifying a coarse grained reconfigurable array having a plurality of tiles operable in parallel;
• mapping the data flows to operations of data through the elements in the tiles;
• determining a schedule to execute the first instructions in the tiles;
• receiving the profile specifying a coarse grained reconfigurable array having the plurality of tiles operable in parallel, wherein the coarse grained reconfigurable array includes latency constraints in propagating data through elements in the tiles;
• mapping the data flows to operations of propagating data through the elements in the tiles;
• determining the schedule to execute the first instructions in the tiles without violating the latency constraints;
• generating a memory map identifying, for each respective memory variable among the plurality of memory variables, one of the tiles that contains a memory location represented by the respective memory variable;
• and
• wherein the data flows are mapped to the operations based on the memory map.

A non-transitory computer storage medium storing instructions which, when executed by a computing device, cause the computing device to perform a method, comprising:

• receiving a program specifying a plurality of memory variables, a plurality of data flows through the memory variables, and first instructions to transform data along the data flows;
• receiving a profile specifying a coarse grained reconfigurable array having a plurality of tiles operable in parallel;
• mapping the data flows to operations of data through the elements in the tiles;
• determining a schedule to execute the first instructions in the tiles without violating the latency constraints;
• receiving the profile specifying a coarse grained reconfigurable array having the plurality of tiles operable in parallel, wherein the coarse grained reconfigurable array includes latency constraints in propagating data through elements in the tiles;
• mapping the data flows to operations of propagating data through the elements in the tiles;
• determining the schedule to execute the first instructions in the tiles without violating the latency constraints, wherein the schedule is configured to identify timing of execution of the first instructions in the tiles;
• generating a memory map identifying, for each respective memory variable among the plurality of memory variables, one of the tiles that contains a memory location represented by the respective memory variable;
• wherein the data flows are mapped to the operations based on the memory map.