Hardware-based Galois multiplication

A method of data processing in a processor, said method comprising:

• fetching, by an instruction fetch unit, instructions to be executed by the processor, wherein the instructions include a Galois multiply instruction including a mode field that specifies a data format applicable to a Galois carryless multiplication and modular reduction operation;
• and
• based on receiving the Galois multiply instruction, an execution unit of the processor executing the Galois multiply instruction based on the data format specified by the mode field, wherein the executing includes:
• multiplying, by a carryless multiplier, operands of the Galois multiply instruction to generate a product;
• a modular reduction circuit receiving the product and determining, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product;
• and
• storing the reduced product to an architected register file of the processor as a result of the Galois multiply instruction.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processor, including:
• an instruction fetch unit that fetches instructions to be executed;
• an architected register file including a plurality of registers for storing source and destination operands;
• and
• an execution unit for executing a Galois multiply instruction, the Galois multiply instruction including a mode field that specifies a data format applicable to a Galois carryless multiplication and modular reduction operation, wherein the execution unit includes:
• a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product;
• and
• a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product, wherein the execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction, and wherein the execution unit executes the Galois multiply instruction based on the data format specified by the mode field.