Computing device and method using multiplier-accumulator

A computing method performed by a multiplier-accumulator, the computing method comprising:

• applying, to a plurality of exclusive negative OR (XNOR) gates corresponding to each of one or more input lines, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is inverted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of an input bit sequence and a weight bit sequence;
• in response to the plurality of XNOR gates receiving signals corresponding to an input bit sequence and a weight bit sequence corresponding to a corresponding input line of the one or more input lines, outputting partial product results between the input bit sequence and the weight bit sequence;
• and
• generating an output in which a correction value is applied to operation results in which the partial product results output from the plurality of XNOR gates are summed,
• wherein the original sequence expressed in 2's complement is inverted to a number system having bit values of only −1 and +1, the input bit sequence and the weight bit sequence are expressed in the number system having bit values of only −1 and +1;
• wherein the applying comprises:
• sequentially receiving an original input sequence expressed in 2's complement of the input bit sequence for each bit position;
• and
• in response to receiving the MSB, applying a signal corresponding to a value in which the logical value of the MSB for the original input sequence is inverted to the plurality of XNOR gates provided to an input line of the one or more input lines corresponding to the input bit sequence.

A multiplier-accumulator comprising:

• an encoder configured to generate a sequence in which a logical value of a most significant bit (MSB) is inverted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of an input bit sequence and a weight bit sequence;
• a plurality of memory cells provided along one or more input lines and configured to output partial product results between the input bit sequence and the weight bit sequence, based on the generated sequence;
• and
• an outputter configured to generate an output based on a summation of the partial product results and one or more correction values,
• wherein the original sequence expressed in 2's complement is inverted to a number system having bit values of only −1 and +1, the input bit sequence and the weight bit sequence are expressed in the number system having bit values of only −1 and +1, and
• wherein the encoder comprises an input encoder configured to:
• sequentially receive an original input sequence expressed in 2's complement of the input bit sequence for each bit position;
• and
• in response to receiving the MSB, apply a signal corresponding to a value in which the logical value of the MSB for the original input sequence is inverted to the plurality of memory cells provided to an input line of the one or more input lines corresponding to the input bit sequence.