Memory device security and row hammer mitigation

An apparatus, comprising:

• a content addressable memory (CAM);
• a memory device;
• and
• control circuitry coupled to the memory device and configured to:
• receive a row activation command having a row address of the memory device;
• responsive to determining that a row counter corresponding to the row address is stored in the CAM, increment a first count of the row counter;
• determine whether the first count is greater than a result of a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC);
• and
• responsive to determining that the first count is greater than the result of the RHT minus the second count:
• issue a refresh command to the row address;
• and
• delete the row counter corresponding to the row address from the CAM.

An apparatus, comprising:

• a content addressable memory (CAM);
• a memory device;
• control circuitry coupled to the memory device and configured to:
• receive a row activation command directed to a row address of the memory device;
• determine whether a row counter corresponding to the row address is stored in the CAM;
• responsive to determining that the row counter is not stored in the CAM and to determining that the CAM is full:
• decrement a plurality of row counters stored in the CAM;
• and
• increment a second count of a CAM decrease counter (CDC);
• responsive to determining that the row counter corresponding to the row address is stored in the CAM, determine whether a first count of the row counter is greater than a difference between a row hammer threshold (RHT) and the second count of the CDC;
• and
• responsive to determining that the first count is greater than the difference between the RHT and the second count, issue a refresh command to the row address.