Power management for system-on-chip

A system-on-chip comprising:

• processing circuitry configured to process input data to generate output data;
• and
• power management circuitry configured to control power management policy for at least a portion of the system-on-chip, in which the power management policy comprises a maximum power mitigation policy, wherein the power management circuitry is configured to restrict throughput of the processing circuitry in response to determining that a number of monitored power-intensive events over an evaluation period exceeds a pre-defined threshold;
• in which:
• the input data comprises input data for a machine learning workload to be performed by the processing circuitry, wherein the machine learning workload implements a convolutional neural network;
• the power management circuitry is configured to control a mode of the maximum power mitigation policy depending on metadata indicative of a property of the input data to be processed by the processing circuitry in the machine learning workload, in which the mode of the maximum power mitigation policy comprises settings for at least one of:
• detection or weighting of the power-intensive events;
• and
• the pre-defined threshold;
• and
• the power management circuitry is configured to determine, based on the metadata associated with the input data to be processed by the processing circuitry, a load/store overhead estimate indicative of an estimated overhead associated with loading the input data or storing the output data, and control the mode of the maximum power mitigation policy based on the load/store overhead estimate, in which the load/store overhead estimate is indicative of an estimated overhead incurred by at least one of:
• a load/store unit configured to control issuing of load/store requests to a memory system;
• an interconnect configured to control routing of memory access requests across the system-on-chip;
• access to on-chip memory storage circuitry;
• access to off-chip memory storage circuitry;
• and
• loss of processing efficiency at the processing circuitry due to load/store delays.