Power source switching circuit and electronic device
AssigneeHonor Device Co., Ltd.
InventorHuarong Jiang
Life of this patent
Estimating the term…
Abstract
A power source switching circuit and an electronic device. The power source switching circuit includes a system power source, a BUCK power supply system, an LDO power supply system, and a power source management chip. The LDO power supply system includes an LDO chip and a first switch circuit, the LDO chip is coupled to the system power source, the LDO chip is in a working state, and the power source management chip is coupled to the LDO chip by using the first switch circuit. The BUCK power supply system includes a BUCK chip and a second switch circuit, the BUCK chip is coupled to the system power source, the power source management chip is coupled to the BUCK chip by using the second switch circuit, and the power source management chip controls a status of the BUCK chip.
Claims18
A circuit, comprising:
- a system power source;
- a power source management chip;
- a low-dropout (LDO) power supply system, comprising:
- an LDO chip coupled to the system power source, wherein the LDO chip is in a working state;
- and
- a first switch circuit, wherein the power source management chip is coupled to the LDO chip by the first switch circuit;
- and
- a BUCK power supply system, comprising:
- a BUCK chip coupled to the system power source;
- and
- a second switch circuit, wherein the power source management chip is coupled to the BUCK chip by the second switch circuit, and the power source management chip is configured to control a status of the BUCK chip, the second switch circuit comprising:
- a second switching transistor, wherein a control terminal of the second switching transistor is coupled to the BUCK chip, and the BUCK chip is configured to control a connection status of the second switching transistor;
- and
- a third switching transistor, wherein a control terminal of the third switching transistor is coupled to a switching channel of the second switching transistor, and the connection status of the second switching transistor controls a connection status of the third switching transistor, and wherein one end of a switching channel of the third switching transistor is coupled to the BUCK chip, and the other end of the switching channel is coupled to the power source management chip,
- wherein both the first switch circuit and the second switch circuit are coupled to the BUCK chip, and the BUCK chip is configured to control one of the first switch circuit and the second switch circuit to be in a closed state.
An electronic device, comprising:
- a power source switching circuit, comprising:
- a system power source;
- a power source management chip;
- a low-dropout (LDO) power supply system, comprising:
- an LDO chip coupled to the system power source, wherein the LDO chip is in a working state;
- and
- a first switch circuit, wherein the power source management chip is coupled to the LDO chip by the first switch circuit;
- and
- a BUCK power supply system, comprising:
- a BUCK chip coupled to the system power source;
- and
- a second switch circuit, wherein the power source management chip is coupled to the BUCK chip by the second switch circuit, and the power source management chip is configured to control a status of the BUCK chip, the second switch circuit comprising:
- a second switching transistor, wherein a control terminal of the second switching transistor is coupled to the BUCK chip, and the BUCK chip is configured to control a connection status of the second switching transistor;
- and
- a third switching transistor, wherein a control terminal of the third switching transistor is coupled to a switching channel of the second switching transistor, and the connection status of the second switching transistor controls a connection status of the third switching transistor, and wherein one end of a switching channel of the third switching transistor is coupled to the BUCK chip, and the other end of the switching channel is coupled to the power source management chip,
- wherein both the first switch circuit and the second switch circuit are coupled to the BUCK chip, and the BUCK chip is configured to control one of the first switch circuit and the second switch circuit to be in a closed state.
Dependencies are inferred from the claim text.