Multi-die system performance optimization

A method, comprising:

• detecting a performance differential between a first circuit and a second circuit of a semiconductor chip package, wherein the first circuit is manufactured to a same design specification as the second circuit, wherein the first circuit has a first intrinsic performance level and the second circuit has a second intrinsic performance level different from the first intrinsic performance level, and wherein a total sum of power allocated to the first circuit to operate at the first intrinsic performance level and allocated to the second circuit to operate at the second intrinsic performance level is equal to a power budget;
• and
• distributing the power budget from a single shared supply voltage between the first circuit and the second circuit to reduce the performance differential between the first circuit and the second circuit, wherein distributing the power budget comprises:
• adjusting, at a first voltage regulator, a first amount of voltage delivered to the first circuit via a first voltage rail from the single shared supply voltage;
• and
• adjusting, at a second voltage regulator, a second amount of voltage delivered to the second circuit via a second voltage rail from the single shared supply voltage.

A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to:

• detect a performance differential between a first circuit and a second circuit of a semiconductor chip package, wherein the second circuit is manufactured to a same design specification as the first circuit, wherein the first circuit is associated with a first intrinsic performance level and the second circuit is associated with a second intrinsic performance level different from the first intrinsic performance level, and wherein a total sum of power allocated to the first circuit to operate at the first intrinsic performance level and allocated to the second circuit to operate at the second intrinsic performance level is equal to a power budget;
• distribute the power budget from a single shared supply voltage between the first circuit and the second circuit to reduce the performance differential between the first circuit and the second circuit;
• adjust, at a first voltage regulator, a first amount of voltage delivered to the first circuit via a first voltage rail from the single shared supply voltage;
• and
• adjust, at a second voltage regulator, a second amount of voltage delivered to the second circuit via a second voltage rail from the single shared supply voltage.