Selectable and hierarchical power management

A method comprising:

• enabling, by a core power management unit of a core of a plurality of cores, power gating of the core by at least:
• receiving a power gating command from software to power gate the core;
• enabling a master bus blocker and a slave bus blocker associated with the core;
• and
• sending a command to a power management unit to power gate the core, wherein the power management unit is connected to the plurality of cores that includes the core;
• and
• disabling, by the core power management unit, power gating of the core, by at least:
• sending a command to the power management unit to disable the power gating and power on the core in response to receiving a wake signal;
• disabling the master bus blocker in response to a powering on signal from the power management unit;
• sending a signal to the software to reboot the core with a warm reset;
• and
• disabling the slave bus blocker in response to a booting complete signal from the software.

One or more non-transitory computer readable storage media storing instructions that, upon execution on a system that includes a plurality of cores, a core power management unit for a core of the plurality of cores, and a power management unit for the plurality of cores, cause operations comprising:

• enabling, by the core power management unit, power gating of the core of the plurality of cores by at least:
• receiving a power gating command from software to power gate the core of the plurality of cores;
• enabling a master bus blocker and a slave bus blocker associated with the core of the plurality of cores;
• and
• sending a command to the power management unit to power gate the core of the plurality of cores;
• and
• disabling, by the core power management unit, power gating of the core of the plurality of cores, by at least:
• sending a command to the power management unit to disable the power gating and power on the core of the plurality of cores in response to receiving a wake signal;
• disabling the master bus blocker in response to a powering on signal from the power management unit;
• sending a signal to the software to reboot the core of the plurality of cores with a warm reset;
• and
• disabling the slave bus blocker in response to a booting complete signal from the software.