Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a substrate including
• a redistribution member, wherein the redistribution member comprises a first surface and a second surface opposite of the first surface, pad structures disposed on the first surface, and a redistribution layer electrically connected to the pad structures,
• an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer,
• a via structure disposed around the interconnect chip and electrically connected to the redistribution layer,
• an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and
• bump structures disposed on the encapsulant;
• and
• a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the pad structures,
• wherein the bump structures include a first bump structure, overlapping at least a portion of the interconnect chip in a first direction that is perpendicular to the second surface, and a second bump structure overlapping at least a portion of the via structure,
• the first bump structure includes a first foil layer that is disposed on the encapsulant and includes a first plating layer disposed on the first foil layer, and
• the second bump structure includes a second foil layer that is disposed on the encapsulant and includes a second plating layer disposed in an opening penetrating through the second foil layer to expose at least a portion of the via structure,
• wherein the redistribution member includes a dielectric layer providing the first surface and the second surface, and
• wherein a thickness of the encapsulant that covers the via structure ranges from about 80% to about 120% of a thickness of the dielectric layer.

A semiconductor package comprising:

• a substrate including
• a redistribution member, wherein the redistribution member comprises a first surface and a second surface opposite of the first surface, and a redistribution layer,
• an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer,
• a via structure disposed around the interconnect chip and electrically connected to the redistribution layer,
• an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and
• bump structures disposed on the encapsulant;
• and
• a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the redistribution layer,
• wherein the bump structures include a foil layer that contacts the encapsulant, a seed layer that contacts the foil layer, and a metal layer that contacts the seed layer, and
• the foil layer, the seed layer, and the metal layer include a same material.