Semiconductor package and method of manufacturing the same

A semiconductor package comprising:

• a first semiconductor chip;
• and
• a plurality of second semiconductor chips vertically stacked on the first semiconductor chip,
• wherein each of the plurality of second semiconductor chips includes:
• a semiconductor layer having a rear surface and a front surface opposing the rear surface;
• a rear bonding pad on the rear surface of the semiconductor layer;
• a through-electrode passing through the semiconductor layer and connected to the rear bonding pad;
• transistors on the front surface of the semiconductor layer;
• a front bonding pad on the front surface of the semiconductor layer;
• a wiring structure connecting the through-electrode to the transistors and formed between the front surface and the front bonding pad;
• and
• a wiring pad between the wiring structure and the front bonding pad, and
• wherein the front bonding pad has a top surface and includes a protrusion extending from the top surface into the wiring pad.

A semiconductor package comprising:

• a first structure;
• and
• a second structure on the first structure,
• wherein the first structure includes:
• a first semiconductor layer having a first front surface and a first rear surface opposing each other;
• a first device layer on the first front surface of the first semiconductor layer and including a first wiring structure;
• a first through-electrode passing through the first semiconductor layer and connected to the first wiring structure of the first device layer;
• and
• a first bonding structure including a first bonding pad on the first rear surface of the first semiconductor layer and connected to the first through-electrode and a first bonding insulating layer on a side surface of the first bonding pad, and
• wherein the second structure includes:
• a second semiconductor layer having a second front surface and a second rear surface opposing each other;
• a second device layer on the second front surface of the second semiconductor layer and including a second wiring structure;
• and
• a second bonding structure including:
• a second bonding pad below the second device layer and bonded to contact the first bonding pad, and
• a second bonding insulating layer bonded to and contacting the first bonding insulating layer,
• wherein:
• the second bonding pad includes a central region and an outer region surrounding the central region, and
• a height of an upper end of the central region is lower than a height of an upper end of the outer region.