Selective bottomless graphene lined interconnects
AssigneeIntel Corporation
InventorsNita Chandrasekhar, Vishal Tiwari, AKM Shaestagir Chowdhury
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Abstract
Embodiments disclosed herein include integrated circuit structures and methods of forming such structures. In an embodiment, an integrated circuit structure comprises a dielectric layer with a first surface and a second surface, and an opening through the dielectric layer. In an embodiment, the opening is defined by sidewalls. In an embodiment, a graphene liner contacts the first surface of the dielectric layer and the sidewalls of the opening. In an embodiment, a conductive material at least partially fills a remainder of the opening.
Claims22
An integrated circuit structure, comprising:
- a dielectric layer with a first surface and a second surface;
- an opening through the dielectric layer, wherein the opening is defined by sidewalls;
- a graphene liner contacting the first surface of the dielectric layer and the sidewalls of the opening, wherein the graphene liner on the sidewalls of the opening does not cover the sidewalls at a bottom region of the opening;
- and
- a conductive material that at least partially fills a remainder of the opening.
An integrated circuit structure, comprising:
- a first trace, wherein the first trace is lined with a first graphene liner;
- a second trace, wherein the second trace is lined with a second graphene liner;
- and
- a via between the first trace and the second trace, wherein the via is lined with a third graphene liner, wherein a bottom of the via contacts the second trace, wherein a bottom surface of the third graphene liner is above the bottom of the via.
A method of forming an integrated circuit structure, comprising:
- forming an opening in a dielectric layer, wherein the opening exposes a top surface of a first conductive material;
- forming a self-assembled monolayer (SAM) over the first conductive material;
- treating the dielectric layer with a plasma;
- forming a graphene liner over sidewalls of the opening, wherein the graphene liner on the sidewalls of the opening does not cover the sidewalls at a bottom region of the opening;
- removing the SAM;
- and
- filling the opening with a second conductive material.
An electronic system, comprising:
- a board;
- a package substrate coupled to the board;
- and
- a die coupled to the package substrate, wherein the die comprises an integrated circuit structure, wherein the integrated circuit structure comprises:
- a first trace, wherein the first trace comprises a first graphene liner that is U-shaped;
- a second trace, wherein the second trace comprises a second graphene liner that is U-shaped;
- and
- a via between the first trace and the second trace, wherein the via comprises a third graphene liner that surrounds a perimeter of the via, wherein a bottom of the third graphene line is above a bottom surface of the via.
Dependencies are inferred from the claim text.