Damascene interconnect structures with low resistance vias for integrated circuits

An integrated circuit (IC) structure, comprising:

• a device layer comprising a plurality of transistors comprising one or more semiconductor materials;
• and
• a plurality of interconnect levels, the interconnect levels further comprising:
• a first line metallization coupled to a terminal of one or more of the transistors;
• a via metallization comprising a fill metal in direct physical contact with the first line metallization over an area including a center of a bottom of the via metallization, and comprising a 2D barrier material in direct physical contact with a sidewall of the fill metal and encircling the area at the center of the bottom of the via metallization, wherein the 2D barrier material comprises a metal chalcogenide or graphene;
• and
• a second line metallization over, and coupled to the first line metallization through the via metallization, wherein the 2D barrier material is at a bottom of the second line metallization, and the second line metallization comprises the fill metal in direct physical contact with the 2D barrier material at the bottom of the second line metallization.