Semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a substrate including an active pattern;
• a source/drain pattern on the active pattern;
• an active contact on the source/drain pattern;
• a lower power line in the substrate;
• a lower contact that vertically connects the active contact to the lower power line;
• a conductive layer between the lower contact and the lower power line;
• and
• a power delivery network layer on a bottom surface of the substrate, wherein
• the conductive layer includes silicon (Si) and a first element,
• the first element includes a transition metal or a metalloid,
• a bottom surface of the lower contact is covered with the conductive layer, and
• a first lower sidewall of the lower contact is covered with the lower power line.

A semiconductor device, comprising:

• a substrate including an active pattern;
• a device isolation layer on the substrate, the device isolation layer defining the active pattern;
• a channel pattern and a source/drain pattern on the active pattern;
• a gate electrode on the channel pattern;
• a gate dielectric layer between the gate electrode and the channel pattern;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer dielectric layer on the source/drain pattern and the gate capping pattern;
• an active contact penetrating the interlayer dielectric layer, the active contact being electrically connected to the source/drain pattern;
• a metal-semiconductor compound layer between the active contact and the source/drain pattern;
• a gate contact penetrating the interlayer dielectric layer and the gate capping pattern, the gate contact being electrically connected to the gate electrode;
• a first metal layer on the interlayer dielectric layer, the first metal layer including a wiring line that is electrically connected to the gate contact;
• a lower power line in the substrate;
• a lower contact penetrating the device isolation layer and extending into the substrate, the lower contact vertically connecting the active contact to the lower power line;
• and
• a power delivery network layer on a bottom surface of the substrate, wherein
• the lower power line includes a body part and a connection part,
• the connection part is connected to the lower contact, and
• the connection part surrounds a first lower sidewall of the lower contact.