Semiconductor package with dummy pads

A semiconductor package, comprising:

• a lower structure;
• and
• an upper structure on the lower structure,
• wherein the lower structure includes:
• a first semiconductor substrate that has a first region and a second region on one side of the first region;
• first through vias on the first region, wherein the first through vias vertically penetrate the first semiconductor substrate;
• first signal pads on the first region, wherein the first signal pads are on the first semiconductor substrate and connected to the first through vias;
• first dummy pads on the second region, wherein the first dummy pads are on the first semiconductor substrate and electrically floated from the first through vias;
• and
• a first dielectric layer on the first semiconductor substrate, wherein the first dielectric layer surrounds the first signal pads and the first dummy pads,
• wherein the upper structure includes:
• a second semiconductor substrate;
• second signal pads on the second semiconductor substrate;
• and
• a second dielectric layer on the second semiconductor substrate, wherein the second dielectric layer surrounds the second signal pads,
• wherein the first dielectric layer and the second dielectric layer are in contact with each other,
• wherein each of the first signal pads and a corresponding one of the second signal pads constitute a single unitary body formed of the same material,
• wherein an arrangement period of the first dummy pads is about 0.5 times to about 1.5 times an arrangement period of the first signal pads,
• wherein the first region is provided in plural, and
• wherein the second region is disposed between the first regions.

A semiconductor package, comprising:

• a substrate;
• semiconductor dies stacked on the substrate;
• and
• a molding layer on the substrate, wherein the molding layer surrounds the semiconductor dies,
• wherein each of the semiconductor dies includes:
• a semiconductor substrate having a device region and a scribe lane region that surrounds the device region;
• first signal pads on the device region, wherein the first signal pads are on an inactive surface of the semiconductor substrate;
• first dummy pads on the device region, wherein the first dummy pads are on the inactive surface of the semiconductor substrate, and the first dummy pads are between the first signal pads;
• second dummy pads on the scribe lane region, wherein the second dummy pads are on the inactive surface of the semiconductor substrate;
• and
• through vias that vertically penetrate the semiconductor substrate, wherein the through vias are connected to the first signal pads,
• wherein the semiconductor dies vertically adjacent to each other are in contact with and bonded to each other,
• wherein top surfaces of the first signal pads are flat, and
• wherein at least one of the second dummy pads has a concave portion recessed toward the semiconductor substrate.