Selective deposition of barrier layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
Life of this patent
Estimating the term…
Loading patent…
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
Estimating the term…
Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.
A method comprising:
A method comprising:
A method comprising:
Dependencies are inferred from the claim text.