Semiconductor device structure with liner layer having tapered sidewall and method for preparing the same

A semiconductor device structure, comprising:

• a first dielectric layer disposed over a semiconductor substrate;
• a second dielectric layer disposed over the first dielectric layer;
• a third dielectric layer disposed over the second dielectric layer;
• a conductive structure disposed in the third dielectric layer, penetrating through the second dielectric layer, and extending into the first dielectric layer;
• a liner layer surrounding the conductive structure, wherein the liner layer has a tapered sidewall in direct contact with the first dielectric layer;
• a spacer structure disposed between the liner layer and the second dielectric layer, wherein the spacer structure is in direct contact with a top surface of the first dielectric layer;
• an inner silicide portion disposed over the conductive structure;
• an outer silicide portion surrounding the inner silicide portion and covering the liner layer;
• and
• an upper plug disposed over the inner silicide portion and the outer silicide portion;
• wherein the spacer structure further comprises:
• an L-shaped liner;
• and
• a porous low-k dielectric layer enclosed by the L-shaped liner and the liner layer.