Gate contact structure

A method, comprising:

• providing a semiconductor structure that includes a gate structure and a source/drain contact over an active region, a gate spacer disposed between the gate structure and the source/drain contact, a selectivity metal layer over the gate structure, and a self-aligned capping (SAC) layer over the selectivity metal layer and the gate spacer;
• depositing an etch stop layer (ESL) and a dielectric layer over the SAC layer;
• forming a gate contact opening through the dielectric layer, the ESL, and the SAC to expose the selectivity metal layer;
• depositing a first glue layer over the gate contact opening;
• depositing a first metal fill layer over the first glue layer without completely filling the gate contact opening;
• etching back the first metal fill layer and the first glue layer until a top surface of the first metal fill layer is lower than a top surface of the ESL but is higher than a top surface of the gate spacer;
• after the etching back, forming a source/drain contact via opening through the dielectric layer and the ESL to expose the source/drain contact;
• depositing a second glue layer over the first metal fill layer in the gate contact opening and the source/drain contact via opening;
• depositing a second metal fill layer over the second glue layer;
• and
• after the depositing of the second metal fill layer, planarizing the semiconductor structure,
• wherein the etching back comprises a dry etch process that uses oxygen, hydrogen, nitrous oxide, nitrogen, a fluorine-containing gas, or a chlorine-containing gas,
• wherein the dry etch process comprises a direct current (DC) bias between about 100 V and about 800 V,
• wherein the dry etch process comprises a radio frequency (RF) power between about 100 W and about 300 W and a temperature between about 20° C. and about 90° C.

A method, comprising:

• providing a semiconductor structure that includes a gate structure and a source/drain contact over an active region, a selectivity metal layer over the gate structure, and a self-aligned capping (SAC) layer over the selectivity metal layer;
• depositing an etch stop layer (ESL) and a dielectric layer over the SAC layer;
• after the depositing of the ESL and the dielectric layer, forming a gate contact opening through the dielectric layer, the ESL, and the SAC to expose the selectivity metal layer over the gate structure;
• depositing a first metal fill layer over the gate contact opening without completely filling the gate contact opening;
• etching back the first metal fill layer;
• after the etching back, forming a source/drain contact via opening through the dielectric layer and the ESL to expose the source/drain contact;
• depositing a second metal fill layer over the first metal fill layer in the gate contact opening and the source/drain contact via opening;
• and
• after the depositing of the second metal fill layer, planarizing the semiconductor structure,
• wherein the etching back comprises use of a fluorine-containing gas, chlorine, hydrogen, oxygen, nitrous oxide, or nitrogen,
• wherein the etching back comprises:
• a bias between about 100 volts and about 800 volts, and
• a temperature between about 20° C. and about 90°.