Package structure having a semiconductor functional structure and redistribution layers (RDLs)

A package structure, comprising:

• an isolation layer with multiple vias, wherein the isolation layer covers a surface of an interconnection layer, each of the vias exposes a respective part of the interconnection layer, and the interconnection layer is arranged on a surface of a semiconductor functional structure;
• N first pads, wherein each of the N first pads is formed by a respective part of the interconnection layer exposed by a corresponding one of the vias, where Nis a positive integer greater than 1;
• N Redistribution Layers (RDLs), wherein each of the RDLs covers the isolation layer and is electrically connected to a respective one of the N first pads;
• and
• a first insulating layer, which is formed on the RDLs and exposes a part area of each of the RDLs;
• wherein the exposed part areas of at least some of the RDLs comprise second pads and third pads, wherein a center point of each of the second pads has a same offset direction and a same offset distance with respect to a center point of a corresponding one of the first pads, the first pads and the second pads are used for testing when the semiconductor functional structure is at different running speeds respectively, and the third pads are used for performing function interaction corresponding to content tested by the second pads;
• wherein the semiconductor functional structure and the package structure located on the semiconductor functional structure form a die;
• some of the first pads are arranged near a first edge of the semiconductor functional structure in parallel along a first direction, and some of the second pads and corresponding ones of the third pads are arranged in parallel along a second direction and are arranged near the first edge, wherein the second direction is perpendicular to the first direction;
• and
• rest of all the first pads are arranged near a second edge of the semiconductor functional structure in parallel along the second direction, wherein the first edge and the second edge are two opposite edges of the semiconductor functional structure, and the second pads and the third pads corresponding to the rest of the first pads are arranged in parallel along the first direction.