Chip including silicon device and III-V semiconductor device on III-V semiconductor layer

A structure comprising:

• a stack of III-V semiconductor layers on a substrate in a first area and a second area, wherein the stack has a III-V semiconductor surface;
• a barrier layer only in the first area on the III-V semiconductor surface;
• a first dielectric material layer only in the first area on the barrier layer;
• a second dielectric material layer in the first area on the first dielectric material layer and in the second area on the III-V semiconductor surface;
• a III-V semiconductor device in the first area and including the barrier layer;
• a silicon device in the second area and including the silicon-based layer;
• and
• an isolation well in the second area and including a doped region within the stack adjacent to the III-V semiconductor surface, wherein the doped region is positioned laterally between undoped regions of the stack below the III-V semiconductor device in the first area and below the silicon device in the second area.

A method comprising:

• forming a stack of III-V semiconductor layers above a substrate in a first area and a second area, wherein the stack has a III-V semiconductor surface;
• forming a barrier layer only in the first area on the III-V semiconductor surface;
• forming a first dielectric material layer only in the first area on the barrier layer;
• forming a second dielectric material layer in the first area on the first dielectric material layer and in the second area on the III-V semiconductor surface;
• forming a III-V semiconductor device in the first area and a silicon device in the second area,
• wherein the III-V semiconductor device includes the barrier layer, and
• wherein the silicon device includes a silicon-based layer extending through the second dielectric material layer to the III-V semiconductor surface in the second area;
• and
• forming an isolation well in the second area and including a doped region within the stack adjacent to the III-V semiconductor surface.