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US 12,733,253 B2Granted
Semiconductor device and fabricating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Ting-Hung Hsu
Life of this patent
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Abstract
An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the MOS region; and source/drain features in the MOS region and separated by the gate region. The gate region includes a fin structure and a nanowire over the fin structure. The nanowire extends from the source feature to the drain feature.
Claims20
A device comprising:
- a dielectric isolation structure disposed on a substrate;
- a first fin structure extending through the dielectric isolation structure, the first fin structure being formed of a first semiconductor material layer;
- a second semiconductor material layer disposed directly on the first fin structure, the second semiconductor material layer interfacing with the dielectric isolation structure, a germanium content in the second semiconductor material layer being greater than a germanium content in the first semiconductor material layer;
- a first elongated semiconductor component disposed over the first fin structure;
- a source/drain feature disposed over the first fin structure and interfacing the first elongated semiconductor component;
- a first gate dielectric layer disposed around the first elongated semiconductor component;
- a first metal layer disposed around the first gate dielectric layer, the first metal layer having a first thickness;
- a second fin structure disposed on the substrate;
- a second elongated semiconductor component disposed over the second fin structure;
- a second gate dielectric layer disposed around the second elongated semiconductor component;
- and
- a second metal layer disposed around the second gate dielectric layer, the second metal layer having a second thickness that is different than the first thickness,
- wherein the first fin structure includes a first anti-punch through feature, and
- wherein the first anti-punch through feature interfaces with the second semiconductor material layer and the dielectric isolation structure,
- wherein the source/drain feature is disposed over and interfaces a top surface of the anti-punch through feature.
12 more elements
A device comprising:
- a dielectric isolation structure disposed on a substrate;
- a first fin structure rising from the substrate and extending through the dielectric isolation structure;
- a semiconductor layer over and interfacing the first fin structure;
- a first semiconductor wire disposed over the semiconductor layer;
- a first gate dielectric layer wrapping around the first semiconductor wire such that the first gate dielectric layer extends between the first semiconductor wire and the semiconductor layer;
- a first metal gate wrapping around the first gate dielectric layer;
- a second fin structure rising from the substrate and extending through the dielectric isolation structure;
- a second semiconductor wire disposed over the second fin structure;
- a second gate dielectric layer wrapping around the second semiconductor wire;
- and
- a second metal gate wrapping around the second gate dielectric layer,
- wherein the first fin structure and the second fin structure comprise silicon,
- wherein the semiconductor layer comprises silicon germanium,
- wherein the first metal gate is spaced apart from the dielectric isolation structure by the first gate dielectric layer,
- wherein the second metal gate is spaced apart from the dielectric isolation structure by the first gate dielectric layer.
12 more elements
A device comprising:
- a dielectric isolation structure disposed on a substrate;
- a first fin structure rising from the substrate and extending through the dielectric isolation structure;
- a silicon germanium layer over and interfacing the first fin structure;
- a germanium wire disposed over the silicon germanium layer;
- a first gate dielectric layer wrapping around the germanium wire such that the first gate dielectric layer extends between the germanium wire and the silicon germanium layer;
- a first metal gate wrapping around the first gate dielectric layer;
- a second fin structure rising from the substrate and extending through the dielectric isolation structure;
- a silicon wire disposed over the second fin structure;
- a second gate dielectric layer wrapping around the silicon wire;
- and
- a second metal gate wrapping around the second gate dielectric layer,
- wherein the first fin structure and the second fin structure comprise silicon,
- wherein the first metal gate is spaced apart from a top surface of the dielectric isolation structure by the first gate dielectric layer.
10 more elements
Dependencies are inferred from the claim text.