Semiconductor device and method of manufacturing the same

A semiconductor device including a first region in which a first MISFET of a first conductivity type is formed and a second region in which a second MISFET of the first conductivity type is formed, the semiconductor device comprising:

• an SOI substrate including a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer;
• a first well region formed in the semiconductor substrate in the first region, a conductivity type of the first well region being a second conductivity type opposite the first conductivity type;
• a first gate insulating film formed on the semiconductor layer in the first region;
• a first gate electrode formed on the first gate insulating film;
• a first impurity region formed in the semiconductor layer located beside the first gate electrode, a conductivity type of the first impurity region being the first conductivity type;
• a second well region formed in the semiconductor substrate in the second region, a conductivity type of the second well region being the second conductivity type;
• a second gate insulating film formed on the semiconductor layer in the second region;
• a second gate electrode formed on the second gate insulating film;
• and
• a second impurity region formed in the semiconductor layer located beside the second gate electrode, a conductivity type of the second impurity region being the first conductivity type,
• wherein a thickness of the second gate insulating film is larger than a thickness of the first gate insulating film,
• wherein a gate length of the second gate electrode is longer than a gate length of the first gate electrode,
• wherein an ON operation and an OFF operation of the first MISFET are controlled by a first gate potential to be supplied to the first gate electrode and a first back gate potential to be supplied to the first well region,
• wherein an ON operation and an OFF operation of the second MISFET are controlled by a second gate potential to be supplied to the second gate electrode in a state where the second well region is electrically floating, and
• wherein an absolute value of a second power supply potential to be supplied to the second impurity region is larger than an absolute value of a first power supply potential to be supplied to the first impurity region.