Method of manufacturing semiconductor device with reduced cell width

A method of manufacturing a semiconductor device, comprising:

• forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate,
• patterning the stacked structure into a fin structure extending along a second direction substantially perpendicular to the first direction;
• forming a sacrificial gate structure extending in a third direction over a first portion of the first semiconductor layers and second semiconductor layers, the third direction being substantially perpendicular to both the first direction and the second direction,
• wherein the sacrificial gate structure includes a sacrificial gate dielectric layer, a sacrificial gate electrode layer formed over the sacrificial gate dielectric layer, and insulating sidewall spacers formed over opposing sidewalls of the sacrificial gate electrode layer;
• forming an interlayer dielectric layer over the insulating sidewall spacers;
• removing the sacrificial gate electrode layer, the sacrificial gate dielectric layer, and a portion of the first semiconductor layers between adjacent second semiconductor layers;
• forming a gate structure extending in the third direction over the first portion of the second semiconductor layers so that the gate structure wraps around the second semiconductor layers,
• wherein the gate structure includes a gate dielectric layer and a gate electrode layer formed over the gate dielectric layer, and the gate dielectric layer extends along opposing sidewalls of the gate electrode layer;
• after forming the gate structure, removing the insulating sidewall spacers from an upper portion of the opposing sidewalls of the gate electrode layer to form trenches on opposing sides of the gate electrode layer;
• and
• filling the trenches with an insulating material.

A method of manufacturing a semiconductor device, comprising:

• forming a stacked structure of first nanosheets and second nanosheets alternately stacked in a first direction over a substrate;
• patterning the stacked structure into a fin structure extending along a second direction substantially perpendicular to the first direction;
• forming a sacrificial gate structure extending in a third direction over a first portion of the first nanosheets the third direction being substantially perpendicular to both the first direction and the second direction,
• wherein the sacrificial gate structure includes an oxide layer, a polysilicon layer formed over the oxide layer, and insulating sidewall spacers formed over opposing sidewalls of the polysilicon layer;
• forming source/drain structures on opposing sides of the sacrificial gate structure;
• forming an interlayer dielectric layer over the source/drain structures;
• removing the polysilicon layer, the oxide layer, and a portion of the first nanosheets;
• forming a gate structure extending in the third direction over the first portion of the first nanosheets so that the gate structure wraps around the first nanosheets,
• wherein the gate structure includes a gate dielectric layer and a gate electrode layer formed over the gate dielectric layer;
• removing the insulating sidewall spacers and the gate dielectric layer from an upper portion of opposing sidewalls of the gate structure to form trenches on opposing sides of the gate structure, wherein a portion of the insulating spacers and a portion of the gate dielectric layer remain at a lower portion of the gate electrode structure and the portion of the insulating sidewall spacers and the portion of the gate dielectric layer contact each other;
• and
• filling the trenches with an insulating material.