Surface-doped channels for threshold voltage modulation
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsiao-Chun Chang, Guan-Jie Shen
Life of this patent
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Abstract
GAAFET threshold voltages are tuned by introducing dopants into a channel region. In a GAAFET that has a stacked channel structure, dopants can be introduced into multiple channels by first doping nano-structured layers adjacent to the channels. Then, by an anneal operation, dopants can be driven, from surfaces of the doped layers into the channels, to achieve a graduated dopant concentration profile. Following the anneal operation and after the dopants are diffused into the channels, depleted doped layers can be replaced with a gate structure to provide radial control of current in the surface-doped channels.
Claims20
A method, comprising:
- forming a superlattice on fins on a substrate, the superlattice comprising doped nanostructured layers and channel layers, wherein the doped nanostructure layers comprise p-type or n-type dopants;
- forming isolation regions on the substrate;
- forming a sacrificial structure on the superlattice;
- etching back the superlattice in source/drain regions, while maintaining the superlattice in a gate region;
- forming inner spacers and epitaxial source/drain regions;
- annealing, the doped nanostructured layers with the inner spacers separating the epitaxial source/drain regions from the doped nanostructured layers to drive in the p-type or n-type dopants from the doped nano-structured layers into the channel layers and form a dopant concentration gradient in each of the channel layers;
- removing the doped nanostructured layers from an annealed channel region;
- forming an inter-layer dielectric over the epitaxial source/drain regions;
- and
- replacing the sacrificial structure with a gate structure.
A method, comprising:
- forming a fin structure on a substrate;
- growing a superlattice on the fin structure, wherein the superlattice comprises first nanostructure layers and second nanostructure layers stacked alternatingly, and wherein the first nanostructure layers comprise first type dopants, wherein the first type dopants comprise p-type or n-type dopants;
- depositing inner spacers on side surfaces of the first nanostructure layers;
- growing epitaxial source/drain regions on side surfaces of the second nanostructure layers;
- forming, by annealing the first and second nanostructure layers with the inner spacers separating the first nanostructure layers and the epitaxial source/drain regions, a dopant concentration gradient in each of the second nanostructure layers;
- removing the first nanostructured layers;
- and
- forming a gate structure around each of the second nanostructure layers.
A method, comprising:
- forming a multi-layer stack that comprises a first nanostructure layer and a second nanostructure layer in contact with the first nanostructure layer, wherein the first nanostructure layer comprises epitaxial silicon germanium (SiGe) doped with first type dopants;
- etching the multi-layer stack to form a fin structure;
- forming an epitaxial source/drain region adjacent to the fin structure, wherein forming the epitaxial source/drain region comprises introducing second type dopants in the epitaxial source/drain region;
- performing, after introducing the second type dopants in the epitaxial source/drain region, an annealing process to concurrently activate the second type dopants in the epitaxial source/drain region and diffuse the first type dopants from the first nanostructure layer to the second nanostructure layer;
- and
- replacing the first nanostructure layer by a gate structure surrounding the second nanostructure layer.
Dependencies are inferred from the claim text.