Multilayer inner spacer for gate-all-around device

A method of manufacturing an electronic device, the method comprising:

• forming a multilayer inner spacer comprising an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate, the superlattice structure comprising a plurality of semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs, the plurality of semiconductor material layers comprising silicon germanium (SiGe) and the corresponding plurality of channel layers comprising silicon (Si), forming the multilayer inner spacer comprising:
• depositing the inner layer on a recessed portion of the plurality of semiconductor material layers;
• optionally etching the inner layer;
• depositing the middle layer on the inner layer;
• etching a portion of the middle layer;
• depositing the outer layer on the middle layer, the outer layer adjacent a source region and a drain region;
• and
• etching the outer layer, wherein the inner layer, the middle layer, and the outer layer are each deposited by a thermal chemical vapor deposition process at a temperature in a range of from 400° C. to 650° C., one or more of the inner layer or the outer layer has a thickness in a range of from 0.5 nm to 2 nm, and the middle layer has a thickness in a range of from 2 nm to 5 nm.

A processing tool comprising:

• a central transfer station comprising a robot configured to move a substrate;
• a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations, the plurality of process stations comprising a chemical vapor deposition (CVD) chamber and an etch chamber;
• and
• a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the substrate between process stations, and to control a process cycle for manufacturing a multilayer inner spacer for a gate-all-around (GAA) device, the multilayer inner spacer comprising an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of the substrate, the superlattice structure comprising a plurality of semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs, the plurality of semiconductor material layers comprising silicon germanium (SiGe) and the corresponding plurality of channel layers comprising silicon (Si), the process cycle comprising forming the multilayer inner spacer by a thermal chemical vapor deposition (CVD) process at a temperature in a range of from 400° C. to 650° C., the thermal CVD process including:
• depositing the inner layer on a recessed portion of the plurality of semiconductor material layers;
• depositing the middle layer on the inner layer;
• and depositing the outer layer on the middle layer, the outer layer adjacent a source region and a drain region, wherein one or more of the inner layer or the outer layer has a thickness in a range of from 0.5 nm to 2 nm and the middle layer has a thickness in a range of from 2 nm to 5 nm.