Semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorSanghoon Uhm
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a bit line on a substrate, a gate electrode on the bit line, a gate insulation pattern on a sidewall of the gate electrode, a channel that contacts an upper surface of the bit line and a sidewall of the gate insulation pattern, an oxide semiconductor pattern that contacts an upper sidewall of the channel, and a contact plug that contacts an upper surface of the channel and an upper surface of the oxide semiconductor pattern. The channel includes an amorphous oxide semiconductor material. The oxide semiconductor pattern includes a crystalline oxide semiconductor material.
Claims20
A semiconductor device comprising:
- a bit line on a substrate;
- a gate electrode on the bit line;
- a gate insulation pattern on a sidewall of the gate electrode;
- a channel that contacts an upper surface of the bit line and a sidewall of the gate insulation pattern, the channel including an amorphous oxide semiconductor material;
- an oxide semiconductor pattern that contacts an upper sidewall of the channel, the oxide semiconductor pattern including a crystalline oxide semiconductor material;
- and
- a contact plug that contacts a top surface of the channel and an upper surface of the oxide semiconductor pattern.
A semiconductor device comprising:
- a bit line on a substrate;
- a gate electrode on the bit line;
- a gate insulation pattern on a sidewall of the gate electrode;
- a channel that contacts an upper surface of the bit line and a sidewall of the gate insulation pattern;
- an oxide semiconductor pattern that contacts an upper portion of a sidewall of the channel;
- and
- a contact plug that contacts a top surface of the channel and an upper surface of the oxide semiconductor pattern,
- wherein a sidewall of the contact plug and a sidewall of the oxide semiconductor pattern are aligned with each other in a vertical direction substantially perpendicular to an upper surface of the substrate.
A semiconductor device comprising:
- bit lines on a substrate, wherein the bit lines each extend in a first direction substantially parallel to an upper surface of the substrate, and wherein the bit lines are spaced apart from each other in a second direction that is substantially parallel to the upper surface of the substrate and intersects the first direction;
- gate electrodes that extend in the second direction on the bit lines, wherein the gate electrodes are spaced apart from each other in the first direction;
- a gate insulation pattern on a sidewall of each of the gate electrodes;
- a channel that contacts an upper surface of each of the bit lines and a sidewall of the gate insulation pattern, wherein the channel includes an amorphous oxide semiconductor material;
- an oxide semiconductor pattern that contacts an upper portion of a sidewall of the channel, wherein the oxide semiconductor pattern includes a crystalline oxide semiconductor material;
- a contact plug that contacts a top surface of the channel and an upper surface of the oxide semiconductor pattern;
- and
- a capacitor on the contact plug.
Dependencies are inferred from the claim text.